1. Field of the Invention
The present invention relates generally to direct digital synthesizers, and more particularly relates to a circuit and method for reducing the harmonic content of signals generated by a direct digital synthesizer.
2. Description of the Prior Art
Direct digital synthesizers (DDS) are well known in the prior art. The block diagram of FIG. 1 illustrates the topology of a known DDS. The DDS of FIG. 1 is capable of generating a sine wave signal with precise control over the phase and frequency of that signal.
Referring to FIG. 1, the DDS includes a frequency value register 2. The frequency value register 2 is operatively coupled to an external digital controller 4, such as a microprocessor. The external controller 4 provides required frequency and phase value information to the DDS. The DDS further includes a phase accumulator circuit 6. The phase accumulator 6 is essentially a counter circuit which cycles between zero and a final value determined by the frequency value received from the frequency register 2 in response to a received DDS phase clock signal.
The phase accumulator 6 generates an address signal which is illustrated in FIG. 2. The address signal is composed of a number of output states which represent equivalent phase values of the DDS output signal. The DDS further includes a sine look-up read only memory (sine ROM) circuit 8. The sine ROM 8 receives the address signal from the phase accumulator 6 and generates a digital sine wave signal in response thereto. The digital sine wave signal is illustrated in FIG. 3. It will be appreciated that while the diagrams of FIGS. 2 and 3 are illustrated graphically, these signals are actually composed of discrete digital values.
The DDS further employs a digital to analog convertor (D/A) 10 to generate an analog sine wave signal. The D/A 10 is responsive to the digital sine wave signal from the sine ROM 8 and generates a corresponding analog sine wave signal.
Because of the discrete nature of the digital sine wave signal and inherent non-linearities associated with the D/A 10, the resulting analog output signal from a conventional DDS is typically rich in harmonic content. Typically, the second harmonic (twice the desired signal frequency) is especially strong.
To eliminate the harmonics from the desired fundamental output signal, a DDS would typically rely on analog filtering techniques. However, given the broadband nature of the DDS, it is often difficult to optimize the filter parameters of a fixed analog filter to properly reduce the harmonics over the full operating frequency range of a DDS. Further, to achieve significant harmonic attenuation, a filter with many poles is required. This filter topology typically introduces signal loss to the desired signal.
As an alternative to conventional filtering, it is also known in the art that discrete signal components, such as harmonics, may be reduced by analog phase cancellation. The block diagram of FIG. 4 illustrates a simplified phase cancellation circuit. Referring to FIG. 4, an input signal including both a desired frequency component and an undesired frequency component is applied to a broad band power divider 11. The power divider 11 equally splits the power of both the desired and undesired signals into two outputs. One output of the power divider 11 is coupled to a narrow band analog phase shift network 12. The phase shift network 12 is designed to provide 0.degree. phase shift to the desired signal and 180.degree. phase shift to the undesired signal.
The second output of the power divider 11 is coupled to an attenuator 14. The attenuator 14 is selected to provide equivalent signal loss to that of the phase shift network 12 at the undesired frequency. In this way, the output level of the undesired frequency component is equal at both the attenuator 14 and phase shift network 12 outputs. These outputs are operatively coupled to a power combiner (adder) 16. The power combiner 16 reinforces in-phase signals and cancels out-of-phase signals. Therefore, the output of the power combiner 16 will feature a slightly reduced desired signal (inherent circuit losses) and a significantly reduced undesired signal level.
Analog phase cancellation has many disadvantages. The analog phase shifter 12 is a narrow bandwidth device. Therefore, the analog phase shift network 12 is difficult to manufacture (tuning adjustments often required) and is only usable over a limited frequency range. Also, the analog phase cancellation circuit often attenuates the desired signal. To overcome these signal loses, additional amplifiers are typically required.